1. Field of the Invention
The present invention relates generally to a numerically controlled oscillator (NCO), and more particularly to jitter compensation in a NCO.
2. Description of Related Art
An NCO may be used to generate a desired clock from a known clock when the ratio between the two clocks is not an exact integer, e.g., when a clock of 3.2 KHz needs to be generated from a clock of 32.768 KHz. FIG. 1A illustrates a prior art NCO. As shown, the NCO 100 may have a register 101 and an accumulator 102. The accumulator may have, e.g., 24 bits. The accumulator 102 may receive an input clock and may be incremented during each pulse of the input clock. The generated clock is the most significant bit (MSB) of the accumulator 102. A step used to increment the accumulator 102 may be stored in the register 101, and may be calculated by the following formula:Step=0x100—0000*output_frequency/input_frequency  (1)
When the value from 0x0 to 0x80—0000 of the accumulator 102 is the same, and the value from 0x80—0000 to 0x100—0000 of the accumulator 102 is the same, the NCO 100 may create a close-to 50% duty cycle clock that toggles high when the accumulator 102 is in the value ranging from 0x80—0000 to 0x100—0000, and toggles low when the accumulator 102 reaches its maximum value and wraps around. The value 0x100—0000 is used because two same edge toggles make up one clock period, hence 0x100—0000=0x80—0000*2.
When the frequency of an input clock is 11.38 KHz, the expected output frequency is 3.2 KHz, and a 5 bit accumulator is used, the step may be calculated as follows according to Equation (1):Step=32*3.2/11.38≈9
For each cycle of the input clock, the accumulator 102 may be incremented by the step from the register 101. The clock at the output of the accumulator 102 may become high when the accumulator value reaches 16, which is the 0x80—0000 value and a MSB threshold, and may become low when the accumulator value exceeds 31, which is the 0x100—0000 value or the maximum value of the accumulator 102.
FIG. 1B illustrates a signal timing reference chart of a prior art NCO. As shown, at time 0, the register 101 has the step value 9, and the accumulator 102 has a value of binary 0. At time 1, or the first input clock pulse, the accumulator 102 may be incremented by the step value 9, and the accumulator value may become 9. Since it is lower than the MSB threshold 16, the MSB value of the accumulator 102 is still binary zero. At time 2, the accumulator 102 may be incremented by the step value 9 again, and its output may become 18. Since it exceeds the MSB threshold 16, the MSB value of the accumulator 102 may change to binary one. This binary one may continue until just before time 5. At time 5, the output of the accumulator 102 may change to 36 and exceed the maximum 31 of the accumulator 102. As a result, the MSB value of the accumulator 102 may drop to binary 0, with a remainder 5 left in the accumulator 102. Thus, at time 6, the beginning of the second cycle, the accumulator 102 may start from the value 5, instead of the value 0 at time 0. The remainder may cause offsets between a reference MSB and the actual MSB, or jitters, as shown in FIG. 1B. From cycle to cycle, the NCO edges may jitter up to 1 full period of the input clock, e.g., 11.38 kHz in the example shown in FIG. 1B.
Thus, the NCO does not create a perfect clock, but a clock that has the correct frequency on average. It may be desirable to provide a method and apparatus for reducing NCO jitter.